Hello all, I have a problem in DPL, I tried to change all insertion diode strategies and change the cell pad value and it didn't work. My config is: # SPDX-FileCopyrightText: 2020 Efabless Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # SPDX-License-Identifier: Apache-2.0 set ::env(PDK) "sky130A" set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" set script_dir [file dirname [file normalize [info script]]] set ::env(DESIGN_NAME) tile set ::env(VERILOG_FILES) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ /home/younis/caravel_tutorial/caravel_example/verilog/rtl/tile/include.v \ /home/younis/caravel_tutorial/caravel_example/verilog/rtl/tile/tile.tmp.v" set ::env(DESIGN_IS_CORE) 1 set ::env(CLOCK_PORT) "clk" set ::env(CLOCK_NET) "clk" set ::env(CLOCK_PERIOD) "20" set ::env(FP_SIZING) absolute set ::env(DIE_AREA) "0 0 2800 3300" ## PDN set ::env(FP_PDN_CORE_RING) 1 set ::env(FP_PDN_VPITCH) 50 set ::env(FP_PDN_HPITCH) 130 set ::env(FP_PDN_VWIDTH) 1.6 set ::env(FP_PDN_CORE_RING_VWIDTH) 1.6 # You can draw more power domains if you need to set ::env(VDD_NETS) [list {vccd1}] set ::env(GND_NETS) [list {vssd1}] #set ::env(FP_PDN_ENABLE_RAILS) 0 ### Macro PDN Connections set ::env(FP_PDN_MACRO_HOOKS) "\ l15.l15.dtag1 vccd1 vssd1 \ l15.l15.dtag2 vccd1 vssd1 \ l15.l15.dtag3 vccd1 vssd1 \ l15.l15.dtag4 vccd1 vssd1 \ l15.l15.dcache1 vccd1 vssd1 \ l15.l15.dcache2 vccd1 vssd1 \ l15.l15.dcache3 vccd1 vssd1 \ l15.l15.dcache4 vccd1 vssd1 \ l15.l15.dcache5 vccd1 vssd1 \ l15.l15.dcache6 vccd1 vssd1 \ l15.l15.dcache7 vccd1 vssd1 \ l15.l15.dcache8 vccd1 vssd1 \ l15.l15.dcache9 vccd1 vssd1 \ l15.l15.dcache10 vccd1 vssd1 \ l15.l15.dcache11 vccd1 vssd1 \ l15.l15.dcache12 vccd1 vssd1 \ l15.l15.dcache13 vccd1 vssd1 \ l15.l15.dcache14 vccd1 vssd1 \ l15.l15.dcache15 vccd1 vssd1 \ l15.l15.dcache16 vccd1 vssd1 \ l15.l15.hmt1 vccd1 vssd1 \ l15.l15.hmt2 vccd1 vssd1 \ l15.l15.hmt3 vccd1 vssd1 \ l15.l15.hmt4 vccd1 vssd1 \ l15.l15.hmt5 vccd1 vssd1 \ l15.l15.hmt6 vccd1 vssd1 \ l15.l15.hmt7 vccd1 vssd1 \ l15.l15.hmt8 vccd1 vssd1 \ l15.l15.hmt9 vccd1 vssd1 \ l15.l15.hmt10 vccd1 vssd1 \ l15.l15.hmt11 vccd1 vssd1 \ l15.l15.hmt12 vccd1 vssd1 \ l15.l15.hmt13 vccd1 vssd1 \ l15.l15.hmt14 vccd1 vssd1 \ l15.l15.hmt15 vccd1 vssd1 \ l15.l15.hmt16 vccd1 vssd1" set ::env(FP_PDN_CHECK_NODES) 0 set ::env(FP_PDN_ENABLE_MACROS_GRID) 1 ## Internal Macros set ::env(VERILOG_FILES_BLACKBOX) "/home/younis/caravel_tutorial/caravel_example/sky130_sram_1kbyte_1rw1r_32x256_8/sky130_sram_1kbyte_1rw1r_32x256_8.v" set ::env(EXTRA_LEFS) "/home/younis/caravel_tutorial/caravel_example/sky130_sram_1kbyte_1rw1r_32x256_8/sky130_sram_1kbyte_1rw1r_32x256_8.lef" set ::env(EXTRA_GDS_FILES) "/home/younis/caravel_tutorial/caravel_example/sky130_sram_1kbyte_1rw1r_32x256_8/sky130_sram_1kbyte_1rw1r_32x256_8.gds" set ::env(SYNTH_STRATEGY) "AREA 1" set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg set ::env(PL_BASIC_PLACEMENT) 0 set ::env(PL_TARGET_DENSITY) 0.7 ## Placement set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1 set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 2 set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2 set ::env(PL_MACRO_CHANNEL) {20 20} set ::env(PL_MACRO_HALO) {10 10} # Maximum layer used for routing is metal 4. # This is because this macro will be inserted in a top level (user_project_wrapper) # where the PDN is planned on metal 5. So, to avoid having shorts between routes # in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. # set ::env(ROUTING_CORES) 12 set ::env(RT_MAX_LAYER) {met4} set env(CELL_PAD) 2 set ::env(DIODE_INSERTION_STRATEGY) 2 # If you're going to use multiple power domains, then disable cvc run. set ::env(RUN_CVC) 1

file a github issue and share

issue_reproducible

. i will look into it

@Vijayan Krishnan sorry, but what do you mean by "issue_reproducible"?

If the flow ends in an error a tarball is automatically created. There is a message in the log about it

@Vijayan Krishnan @Matt Liberty https://github.com/The-OpenROAD-Project/OpenLane/issues/1186