@Tim Edwards I’m seeking to regenerate the whole chip (user_project_wrapper + management_core_wrapper) on my local PC. But as I progress it sounds more confusing to me. For example: 1. What are

make ship

,

make final

and

make generate_fill

actually doing? Is there any full documentation for all make commands/recipes? 2. What’s difference b/w MCW and Caravel itself?

I am not exactly sure what the divisions are, but I know that

make ship

prepares the top level GDS prior to fill generation and adding the seal ring, which are the two steps necessary to prepare for submitting to the foundry.

make final

runs a script called

compositor.py

which in turn generates the final GDS including fill generation and seal ring. I'm not sure what purpose

make generate_fill

has when called from the caravel Makefile.

management_core_wrapper

I believe that you only need to insert the steps

make ship

and

make final

. (2) The management core wrapper is the CPU inside Caravel. We made it into a separate repository so that it can be replaced with any pin-compatible CPU. It works much like the user project wrapper: The CPU is synthesized separately, and then the Caravel chip is assembled by putting together the base layout and adding the user project wrapper and the management core wrapper.

Thanks a lot @Tim Edwards for the reply. Today I tried many different things and finally here is MY VERSION of the recipe (which I do not insist that it is correct, but it is working as I expected):

export CARAVEL_LITE=0
export PDK=sky130A
export PROJ_ROOT=$HOME/Desktop/caravel_user_project
export CARAVEL_ROOT=$PROJ_ROOT/caravel
export MCW_ROOT=$PROJ_ROOT/mgmt_core_wrapper
export OPENLANE_ROOT=$PROJ_ROOT/new_openlane
export PDK_ROOT=$OPENLANE_ROOT/pdks
git clone <https://github.com/efabless/caravel_user_project.git> $PROJ_ROOT
cd $PROJ_ROOT
make setup
# In case you modified the design run the following command(s):
# make user_proj_example; make user_project_wrapper
cp caravel/verilog/rtl/caravel.v verilog/rtl/
cp caravel/mag/caravel.mag mag/
make ship
klayout gds/caravel.gds

Do you have any workarounds for those

cp

commands? I mean:

cp caravel/verilog/rtl/caravel.v verilog/rtl/
cp caravel/mag/caravel.mag mag/

I don’t know why

make ship

does not search the

$CARAVEL_ROOT

to find

.v

and

.mag

files of the Caravel! Am I missing something?