Hey, Can anyone help me why are the pins getting staggered and extended here. but the flow passes for the design. And does that cause any antenna violations?

What you have highlighted is a via4. met4 - met5 connection. These 8 vertical paths are vssd1, vssd2, vssa1, vssa2, vccd1, vccd2, vdda1, vdda2.

The first image is for the

golden wrapper

and as you can see the layers are as

vssa2

,

vdda2

,

vssa1

,

vdda1

,

vssd2

,

vccd2

,

vssd1

,

vccd1

. but for the user project wrapper i'm getting the change in the arrangement of the pins i.e.

vssa2

,

vssa1

,

vssd2

,

vdda2

,

vdda1

,

vccd2

,

vssd1

,

vccd1

. and due to this i'm getting XOR violations too as the power pins are changed. any solution how can i match them with the one in

golden_wrapper

What version of

mpw_precheck

and what version of

caravel_user_project

are you using? (check the commits).

mpw-6c (

b30e779

) 6728dfeef76884ce996e3f3f9eff422a123b3ecd for mpw_precheck and cd4f35df25e15f6cb35cd3bd777f8779566491e8 for

caravel_user_project

.

I was facing this issue in latest openroad tool-set not in mpw-6c ? This had two issue, 1. Power pins where interchanged. this fix should be available in in latest openlane https://github.com/The-OpenROAD-Project/OpenLane/pull/1109 2. There is small drift in PDN CORE Ring, We need update following value in config.tcl set ::env(FP_PDN_CORE_RING_HOFFSET) {12.45} set ::env(FP_PDN_CORE_RING_HSPACING) {1.7} set ::env(FP_PDN_CORE_RING_HWIDTH) {3.1} set ::env(FP_PDN_CORE_RING_VOFFSET) {12.45} set ::env(FP_PDN_CORE_RING_VSPACING) {1.7} set ::env(FP_PDN_CORE_RING_VWIDTH) {3.1}

Hi, The PDN Power rings order was changed successfully, but still i'm unable to debug why am I getting extensions of the pins as depicted in the image.

I don't see this as issue, Power hook looks be good .. Did you analysis the user_project_wrapper.xor.gds inside the local pre-checker output directory

the user project wrapper.xor.gds looks like this inside precheck results: there are no power pins in them.

XOR check only User IO ring against golden reference. Look like there is some offset in core ring?. Cross-check Golden Reference : user_project_wrapper_empty_erased.gds and Your Project IO Ring: user_project_wrapper_erased.gds. These files will be available inside pre-checker/output folder