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Could anyone suggest a good open source 'system verilog' simulator?

# caravel

Binoy B

06/21/2022, 12:48 PM

Could anyone suggest a good open source 'system verilog' simulator?

Simon Waid

06/21/2022, 12:59 PM

icarus should support some system verilog. Not sure though how many features http://iverilog.icarus.com/

Tim Edwards

06/21/2022, 1:03 PM

iverilog has pretty marginal support for SV. It depends a lot on just how much system verilog syntax is in the RTL code. Don't expect too much of it. . .

Tomasz Bialas

06/21/2022, 2:07 PM

Not always fully SV compliant but Verilator does a good job https://www.veripool.org/verilator/

Binoy B

06/23/2022, 5:11 AM

Thanks

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