need these. Four resistors total, two on either side of the connections between VSSIO and VSSIO_Q on the first pad, and between VDDIO and VDDIO_Q on the second. Note that this does not solve the problem by itself, but with the right flattening of cells on GDS input, this can be made to work to get an LVS clean result on the overlay cells.
RTimothyEdwards/open_pdks
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