Hi. Has anyone tried multi-core gate-level simulation? For example, using verilator? My RTL testbench takes half an hour, and the gate-level simulation seems to be taking forever 😅

If you can provide a test case it would be useful to help the maintainers of verilator and community members to speed things up.

They can take the example testbenches and have them be run by verilator instead of iverilog.