Excuse me, when I did the precheck, I met the GPIO failure. But our design doesn't use these GPIOs, do I need to assign values to these ports anyway?

You must edit user_defines.v. Don' t keep it as default.

even I don't use the GPIOs?

Yes, that are the default status of gpio at power up. No mater you use it or not, gpios are on the chip.

So do you know what value should I assign to these GPIOs? Can I just set them to 0?

One of the macro above:

GPIO_MODE_MGMT_STD_INPUT_NOPULL    
 GPIO_MODE_MGMT_STD_INPUT_PULLDOWN  
 GPIO_MODE_MGMT_STD_INPUT_PULLUP    
 GPIO_MODE_MGMT_STD_OUTPUT          
 GPIO_MODE_MGMT_STD_BIDIRECTIONAL   
 GPIO_MODE_MGMT_STD_ANALOG         

 GPIO_MODE_USER_STD_INPUT_NOPULL    
 GPIO_MODE_USER_STD_INPUT_PULLDOWN  
 GPIO_MODE_USER_STD_INPUT_PULLUP   
 GPIO_MODE_USER_STD_OUTPUT         
 GPIO_MODE_USER_STD_BIDIRECTIONAL   
 GPIO_MODE_USER_STD_OUT_MONITORED   
 GPIO_MODE_USER_STD_ANALOG

OK, do I need to harden my chip again after I modify user_define.v?

As Tim said, I think that happen on the

tape out

step. And there will be a script replacing the configuration of caravel, which isn't harden by us. So it's not necessary to harden our design again. Just place the file in the project and let the script find it, that is enough.

ok thank you very much!

@b224hisl you don’t use any of the caravel gpio pads? What does your chip do? BTW, you can find the previous default gpio settings at

caravel/verilog/rtl/user_defines.v

here is my user_project_wrapper.v

module user_project_wrapper #(

parameter BITS = 32

) (

``ifdef USE_POWER_PINS`

inout vdda1,    // User area 1 3.3V supply

inout vdda2,    // User area 2 3.3V supply

inout vssa1,    // User area 1 analog ground

inout vssa2,    // User area 2 analog ground

inout vccd1,    // User area 1 1.8V supply

inout vccd2,    // User area 2 1.8v supply

inout vssd1,    // User area 1 digital ground

inout vssd2,    // User area 2 digital ground

``endif`

// Wishbone Slave ports (WB MI A)

input wb_clk_i,

input wb_rst_i,

input wbs_stb_i,

input wbs_cyc_i,

input wbs_we_i,

input [3:0] wbs_sel_i,

input [31:0] wbs_dat_i,

input [31:0] wbs_adr_i,

output wbs_ack_o,

output [31:0] wbs_dat_o,

// Logic Analyzer Signals

input  [127:0] la_data_in,

output [127:0] la_data_out,

input  [127:0] la_oenb,

// IOs

`input [

MPRJ_IO_PADS-1:0] io_in,

`output [

MPRJ_IO_PADS-1:0] io_out,

`output [

MPRJ_IO_PADS-1:0] io_oeb,

// Analog (direct connection to GPIO pad---use with caution)

// Note that analog I/O is not available on the 7 lowest-numbered

// GPIO pads, and so the analog_io indexing is offset from the

// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).

`inout [

MPRJ_IO_PADS-10:0] analog_io,

// Independent clock (on independent integer divider)

input   user_clock2,

// User maskable interrupt signals

output [2:0] user_irq

);

io_in

,

analog_io

come from the gpio cells.

io_out

goes to the gpio cells. Do you use any of these signals in your design?

oh, of course, but I don't know what values to set for these GPIOs in user_define.v

These are probably the ones you should be interested in

`define GPIO_MODE_USER_STD_INPUT_NOPULL    13'h0402      <- straight input (input should be high or low - no connection not allowed)
`define GPIO_MODE_USER_STD_INPUT_PULLDOWN  13'h0802      <- input that goes low with nothing connected
`define GPIO_MODE_USER_STD_INPUT_PULLUP    13'h0c02      <- input that goes high with nothing connected
`define GPIO_MODE_USER_STD_OUTPUT          13'h1808      <- for outputs
`define GPIO_MODE_USER_STD_BIDIRECTIONAL   13'h1800      <- for bidirectional signals
`define GPIO_MODE_USER_STD_OUT_MONITORED   13'h1802
`define GPIO_MODE_USER_STD_ANALOG          13'h000a      <- for analog signals

ok thank you!