Also, I thought I'd try synthesizing a VexRiscv design I've got, but

abc

is taking a very long time. Most of the synthesis was done in just a few minutes, but it's been stuck on

Executing ABC

for just over six hours now. Is that normal, and if not, what can I do to improve it? I do see that

yosys-abc

has been running at 100% for a while, and it is now listed as having

366:10.49

running time now.

File github issue with source rtl. Try other

SYNTH_STRATEGY

like DELAY0/1/2 etc.,

I filed an issue at https://github.com/The-OpenROAD-Project/OpenLane/issues/1514

mistake. its

SYNTH_STRATEGY

Thanks. I'm trying that now. I was adapting the inverter example, which is why some fields were missing.

I assume you have caches in the VexRiscV design; synhesis of big SRAM blocks that are not hard instantiated instances are know to overwhelm yosys and P&R.

That's the current theory. I've been trying to get OpenRAM to generate the tag memories, but I may switch to building them with DFFRAM. I've created memory libfiles for Yosys that should be able to infer the correct blocks.