Hi, <@U016EM8L91B> <@U017X0NM2E7> <@U01819B63HP> Excuse me, I have two inquires What does it mean th...
a
Hi, @Tim Edwards @Mitch Bailey @Stefan Schippers Excuse me, I have two inquires What does it mean this error! Is there a way to move/highlight/zoom on a net in the layout? for example, Net: /bg__pnp_group_0//bgpg__pnp_0/a_26_26
m
You may be using an older version of netgen. @Tim Edwards has recently made some changes to eliminate
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Circuit 2 parallel/series network does not match Circuit 1
From your report, it looks like the collector node of 2 pnp are not connected as expected. In the schematic, their connected to ground, but in the layout they are not. I’m not aware of any lvs error probing feature currently.
I think magic gets confused sometimes with what it considers to be irregular layouts. Your
bgpg__pnp
device is where the pnp device is recognized, but there are no ports at this level and multiple met1. Ideally all these connections would be merged when doing the hierarchical extraction. I’ve found that flattening cells that contain devices but do not have text gives better results. You can look at the extracted spice file to see what subckts have magic generated port names like
w_1242_323#
. If you’re running LVS on the gds, before
gds read
in magic, try
gds flatglob bgpg__pnp
t
@Ahmed Reda and @Mitch Bailey: When I extracted the circuit, I got this in the extracted (layout) netlist:
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.subckt bgpg__pnp w_153_153# a_330_330#
X0 a_26_26# w_153_153# a_330_330# sky130_fd_pr__pnp_05v5 area=0p
.ends
I will treat this as an error in magic's extraction. Fortunately, it has an easy workaround, which is to label the emitter, collector, and base with pins inside the bipolar device. Then it extracts as:
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.subckt bgpg__pnp E B C
X0 C B E sky130_fd_pr__pnp_05v5 area=0p
.ends
And then I get a unique match for the circuit. Note that there's an error in the cascode cell where the input pins are both labeled
inn
. This can cause a problem if you don't use
extract unique
, as the extraction of the circuit will virtually connect the two pins otherwise. But the main issue here is the missing collector pin in the PNP extraction.
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a
@Tim Edwards @Mitch Bailey Thanks you. The Circuits match uniquely.
m
LVS matches, but the report shows property errors. Can you try with the latest version of netgen?
a
Yeah, i see. can you send me a guidance commands to upgrade the netgen to latest version! please
m
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git clone <https://github.com/RTimothyEdwards/netgen.git>
cd netgen
./configure --prefix=<install_path>
make 
make install
If you want to install to
$HOME/local/bin
then
<install_path>
=
$HOME/local
.
a
@Mitch Bailey Hi, I would like to inform you that:- Netgen has been updated. Many property errors have been fixed and some of them have not. However, the simulation results of the extracted spice are relatively matched with the simulation results of the schematic circuit. I suppose that the rest property errors did not impact the extracted spice.
m
Great! Some suggestions, 1. One of your dummy mos has an L=1 while the others have L=4. 2. Sometimes size errors show up because 2 cells are placed exactly on top of each other. This can happen in the layout and the schematic. 3. Your bipolar devices are not extracting with L and W.
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t
Bipolars are supposed to be extracting with area, I think, but they aren't and I need to figure out why. The bipolar SPICE models, however, are specific to the couple of layouts (0.68um x 0.68um emitter layout, and 3.4um x 3.4um emitter layout) and so the emitter size is contained within the model.
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