Another question, is there any solution to simulate the top io in

verilog/dv/xxx/xxx_tb.v

. They are

inout

port and I always got

z

or

x

, if I connected them to other module or write to them.

I'm simulating it using io_ports_tb.v and it works almost fine... It needs quite some time to finish configuration of the GPIOs; maybe 1 ms.

Yes,

io_ports_tb.v

does work fine. But it's too simple. How about connect the

inout

GPIO to other module and review the waveform on

gtkwave

?

You need to specify the configurations in io_ports.c and use mprj_io for connections.

No effect? are you sure?

Almost. For example, io_ports.c is configuring GPIOs 0 thru 7 as outputs. I specified this config in user_defines.v and commented this config in io_ports.c . The test failed :)

@jeffdi Is that a bug? We'd better have a correct simulation env to ensure the wrapper of the design is correct.

I think Jeff is busy enough as it is 😂

for local Simulation to work, you need to modify file:mgmt_core_wrapper/verilog/includes/includes.rtl.caravel From: -v $(CARAVEL_PATH)/rtl/user_defines.v To: -v $(USER_PROJECT_VERILOG)/rtl/user_defines.v My local simulation work fine with this change

yes, I remember seeing something including it in the caravel verilog when wandering around the rtl: https://github.com/efabless/caravel/blob/5f4a5b7b46f05d476622ab9d9c24eb5721ef495a/verilog/rtl/caravel_netlists.v#L24