One gentleman contacted me after mpw6 and 7 tape-out. There is an issue with Yosys. It connects all the unconnected nets to ground. This could result in shorts. Do we have to fix this issue in our design? Can anyone from efabless/Openlane comment on this?

Known issue. Can cause fatal errors when connecting outputs of macros where you assume one output is not connected to anything. Does it connect all unconnected nets to ground or just the ones that have been declared as wires? Does setting ``default_nettype none` make a difference?

`default_nettype none is already there in user_project_wrapper.v. Still it happens. Unconnected nets which are declared as wires has this issue. Do we have to take care of this? Precheck don't flag this as problem.

Precheck cannot check this. gate level verilog simulation should give you unexpected results. Yes, you should take care of this.

Grounding an unused input seems begnin. Ground an unused output is a serious error. Do you have an example of this?

Last year’s SCSS had one. https://efabless/projects/474

io_out[8,9,14,15,25,26,27]

are all outputs unconnected in the

user_proj_example

rtl, but tied to ground in the gl verilog. These are shared with other analog macros in

user_project_wrapper

.

@Vijayan Krishnan can you reproduce this issue and package a test case?

make extract-parasitics has a dependency on iverilog. See the error below. It would be good to capture this at documentation. File "/home/aloke/projects/uP16_efabless/venv/lib/python3.10/site-packages/pyverilog/vparser/parser.py", line 2309, in preprocess self.preprocessor.preprocess() File "/home/aloke/projects/uP16_efabless/venv/lib/python3.10/site-packages/pyverilog/vparser/preprocessor.py", line 86, in preprocess subprocess.call(cmd) File "/usr/lib/python3.10/subprocess.py", line 345, in call with Popen(*popenargs, **kwargs) as p: File "/usr/lib/python3.10/subprocess.py", line 969, in init self._execute_child(args, executable, preexec_fn, close_fds, File "/usr/lib/python3.10/subprocess.py", line 1845, in _execute_child raise child_exception_type(errno_num, err_msg, err_filename) FileNotFoundError: [Errno 2] No such file or directory: 'iverilog' make: * [Makefile305 extract-parasitics] Error 1

Please check this thread: https://open-source-silicon.slack.com/archives/C02K4RD241Y/p1669059700895009?thread_ts=1669041568.020849&cid=C02K4RD241Y

The unused outputs which are declared as wires are connected to sky130_fd_sc_hd__conb_1 sky130_fd_sc_hd__conb_1 soc_config_205 (.VGND(vssd1), .VNB(vssd1), .VPB(vccd1), .VPWR(vccd1), .LO(net205)); <--- I think it should be fine, right?

If there are no other connections to the output signal, there may not be a problem. When the output signals are shared between macros, you need to check.