**************************************************** <!channel> We are happy to finally announce readiness to resubmit MPW-7 projects. We are asking all project owners who met the original submission deadline to resubmit their projects on the Efabless platform for MPW-7 by December 5th at 11:59 PST. PROJECT RESUBMISSION As part of resubmission, please complete the following steps: 1. Update your project to include

verilog/rtl/user_defines.v

. ◦ Within this file, you will need to specify the power-on default configuration for each GPIO pad for your project ◦ The configuration determines whether the pad is connected to the user or management area, digital vs analog, input vs output, and pull-up or pull-down resistors for inputs. ◦ Please see the Section - GPIO Configuration 4 of the Caravel User Project documentation for further information. ◦ You can find a copy of

user_defines.v

here. You need to modify the configuration for each IO based on your project’s IO usage. 1. Run chip-level static timing analysis for your project integrated in updated Caravel design. ◦ Post-layout static timing analysis has been updated to catch the timing violations seen in MPW-2 silicon. ◦ A new script has been created to run the updated timing analysis flow ◦ Please see the documentation for how to run timing on existing projects ( or Step 4 of the Quickstart documentation for new projects ). ◦ A summary of timing results is provided at the end of the flow. ◦ If you identify a timing issue with your design - please post your issue on the Slack channel #timing-closure and we will provide guidance on options to address timing issues with Openlane. 1. Rerun mpw_precheck and tapeout on the Efabless platform for your MPW-7 project. ◦ mpw_precheck includes an additional check to verify that user_defines.v has been properly provided for your project. ◦ tapeout will include the updated Caravel design correcting issues found with MPW-2 silicon testing. PROJECT SELECTION Projects that complete resubmission by the deadline will be selected based using the lottery process based on their original submission date. Thank you again for your continued patience, encouragement and support for this program. -- The Efabless Team ****************************************************

@Matt Venn Please share the steps to follow for re-submission. Question I've, 1. whether we need to pull latest updates from caravel_user_project? 2. Just update

user_defines.v

and run timing script? Thanks in advance!!!

@jeffdi do you have the git instructions for pulling caravel?

I think I should rebase the history and force push my repo, because the gds I had push is too huge. It will larger than 1GB and github will reject it. If I do so, I could not update on the efabless platform. The git history has been changed.

@jeffdi I see MPW-7 Precheck fails with exception for Klayout FEOL check. Look like script not able to find sky130B.drc file ? Looks to be efabless server side issue .. I thought MPW-7 will use sky130A for tapeout ? My local precheck run is clean.

@Dinesh A If we create a new project from the newest template, and

make setup

, we are using sky130A as default. So, should we create a new repo to resubmit @jeffdi

The instructions are listed here… https://caravel-user-project.readthedocs.io/en/latest/#running-timing-analysis-on-existing-projects

Could you please tell the date of the mpw-8 shuttle?

It just opened.

Alright, thanks~!

My understanding is that

io_oeb

also need to be set according to the

user_defines.v

for the pins you want to enable output for.

Is user_defines.v part of repo? If git clone shall we get it?

Yes @Lab Lecture https://github.com/efabless/caravel_user_project/blob/main/verilog/rtl/user_defines.v Create your own by copying and edit as per your need

Hi @jeffdi, @Tim Edwards, for predefining GPIO config of a caravan analog project in user_defines.v, should gpio_noesd contacts be considered the same as

GPIO_MODE_USER_STD_ANALOG

? One such example is attached where I use gpio_noesd in place of gpio_analog.

@Soumil Jain:

gpio_noesd

and

gpio_analog

both make direct connections from the chip core to the pad. In both cases you want to shut down both the digital input and output buffers, so

GPIO_MODE_USER_STD_ANALOG

is the appropriate mode. (For the record,

GPIO_MODE_MGMT_STD_ANALOG

is exactly the same setting, since "user control" or "management control" has no meaning unless at least one of the digital buffers is turned on).

"*Update your project to include verilog/rtl/user_defines.v*" - mean what? We have to `include "user_defines.v" in user_project_wrapper.v? OR We have to include in user_project_wrapper config.tcl as ## Source Verilog Filesset ::env(VERILOG_FILES) "\ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ $script_dir/../../verilog/rtl/user_defines.v \ $script_dir/../../verilog/rtl/user_project_wrapper.v"

As per re-submission steps no where mentioned to add

user_defines.v

as ``include` file. @Lab Lecture Read step 1 again.

@Vijayan Krishnan I have quoted the step 1 in bold letters. I have a confusion. If you are not sure about the answer let others comment.

I don't think there is any need to ``include` it

Hi @Lab Lecture you have to add that file to your repo and edit it

oh yes, sorry I can see now how my reply was poorly worded, what I meant was that I don't think it has to be 'included from your own rtl, as it gets processed by a separate tool.

@Matt Venn I don't think "adding that file to your repo" is enough. How can it harden into the design?

@Ruige Lee it seems that the file is getting processed as part of the signoff flow in caravel https://github.com/efabless/caravel/blob/9438031c42152d4b31caa5cbc91e1262a38e4bc0/Makefile#L1162

@Ruige Lee: The file gets processed as part of the "top level assembly". There is a script that reads the file and creates the blocks of constant bits that define the power-on defaults for each of the GPIO pins. This happens at the same time as the user project is dropped into the caravel chip and everything is prepared for tape-out.

So the configuration will never work in simulation, you' re right @Muhammad Usama Zubair . https://open-source-silicon.slack.com/archives/C016G7Z8GDR/p1669122259747649?thread_ts=1669121439.818389&amp;cid=C016G7Z8GDR

I am able to run precheck successfully locally and on efabless platform. And, was able to tapeout successfully on efabless. Thanks to everyone for your help and suggestions.