Does anyone know a good way to view netlists as schematics?

Getting a schematic from a netlist is very similar to getting a C++ program by disassembling machine code. It can be done but you get an array of interconnected components. A netlist tells you all the connections but there is no informatilon on the position of transistors/ standard cells, so you get something really hard to understand, see picture, showing an imported schematic of a buffer standard cell. In many cases you just want to simulate the spice netlist within a parent schematic, in this case create an empty symbol with matching I/O ports and import the netlist as text, see second picture.

You might find this useful: https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/21588/creating-a-schematic-file-from-a-netlist-file Note that the discussion is 10+ yrs old. I am guessing it’s still relevant.

Also from concept,

spicevision

, which I use daily and highly recommend.

@Amit Varde @Mitch Bailey It seems these are commercial tools, right?

Yep, it’s commercial, but relatively inexpensive compared to other EDA, IIRC. Haven’t come across any open source tools yet, although @Tim Edwards did have a student present at WOSET a couple years ago. Article 13 https://woset-workshop.github.io/WOSET2020.html

Look at this. For digital it works nicely, also for analog, if you find yourself a SPICE-to-JSON converter. It would be cool to have someone write and opensource such a conversion tool. https://github.com/nturley/netlistsvg

@Zeyi Wang One common use case is when you have a subcircuit drawn as a schematic. When you have a layout for this block you get a netlist with parasitic elements included, and in some cases you want to replace your schematic sub block with the layout extracted netlist. By the way this is how standard cells in sky130 are simulated with xschem. There are no schematics for the standard cells, only netlists. Xschem generates the instance call (like:

x5 IY B VSS VSS VCC VCC net2 sky130_fd_sc_hd__nor2b_1

. then a file is included where the subcircuit is defined as a netlist: .include /home/schippes/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice where the file contains the nor2b_1 cell:

...
...
.subckt sky130_fd_sc_hd__nor2b_1 A B_N VGND VNB VPB VPWR Y
X0 a_74_47# B_N VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=420000u l=150000u
X1 Y a_74_47# VGND VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X2 VGND A Y VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X3 a_74_47# B_N VGND VNB sky130_fd_pr__nfet_01v8 w=420000u l=150000u
X4 VPWR A a_265_297# VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X5 a_265_297# a_74_47# Y VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
.ends
...
...

The first image shows a opamp symbol with corresponding schematic (on the right): By adding a

spice_sym_def

attribute to the symbol (second picture) xschem will include the specified file instead of netlisting the sub-schematic. When including a netlist you must double check the port order of the instance call generated by xschem when doing the netlist matches the port order of the netlist subcircuit. Another way to avoid netlisting a sub schematic is to descend onto a symbol and change

type=subcircuit

to

type=primitive

. Primitives will be considered by xschem as terminal symbols, and no sub-schematic (if any) is included in the netlist. It is your duty to include a file with the definition of the block. This is very similar to compiling a program that uses a function defined in another file. You must tell the compiler where this file is to be able to generate an executable program.

Thanks @Harald Pretl. Looks like all we need is a spice to json converter and then svg to xschem!

The problem with the summer internship ASG project was that it had a long way to go. . . Over the summer, the student worked on the problem of organizing digital gates into a schematic, which is a bit easier problem because for the most part the logic flows left to right. Analog structures have lots of different variations, so it really requires some understanding of the circuit and its intent to understand how best to arrange it into a sensible and readable schematic.

@Tim Edwards I think the trick is to try to reuse frameworks to ease the work like

netlistsvg

did (using

elkjs

). It produces quite nice-looking digital circuits, and the analog ones seem OK, but of course, there is a long way to something like SpiceVision.

@Zeyi Wang, Yes, both tools I recommended are commercial tools. I have made some attempts in the past - using free canvas libraries and commercial tools - to build my own tools/scripts/plugins. While it might be a “correct” representation, it may not be useful for sizable schematics and too much manual work might be needed to make it useful. I gave up on that eventually. I never had the opportunity to use the Concept Engr tools.

Hey folks I really appreciate you taking the time to answer my question! 🙇 🙏

@hsank developed a schematic viewer for netlists of standard cells called "_schematic.tcl", but it only works for most of them, it fails on more complex ones. This is my current work-document for the topic: https://docs.google.com/document/d/1C7XiXJoez5nCElSHSfOlc-AOplQf5dwQwnZLH5FogM4/edit

@Philipp Gühring Thanks for the info!

Also, Verilog netlists can be viewed with yosys. You would use the read_verilog command, and then show. This generates a graphviz .dot file, which can be viewed with xdot. The results might be impractically huge for an entire design, there are ways for selecting a part of it, like a single node and a cone of its outputs