For the Sky130 process, Is there any documentation about transistor mismatch vs. transistor gate area?

Are you talking about process variation or LVS comparison? LVS compares transistor L and W which is indirectly area.

Process variation

Mismatch (in the form of standard deviation of process parameters, like oxide thickness, threshold, ..) usually is inversely proportional to the square root of the gate area. see for example the expression for vth0 in the nfet_01v8 model, note the division by sqrt(l*w*mult).

+ vth0 = {0.5190093+MC_MM_SWITCH*AGAUSS(0,1.0,1)*(sky130_fd_pr__nfet_01v8__vth0_slope/sqrt(l*w*mult))}

This means bigger devices will match better. You can enable mismatch in ngspice on the sky130 process by using corner

tt_mm

. Every run will pick random values for critical process parameters for every single transistor in the netlist. By collecting data of multiple runs you can calculate the distribution of your output variables.

Stefan thankyou for your guidance. It is much appreciated.