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is there a way to specify a clock port as one wire in a bus? like io_in[0] ? <@U018LA3KZCJ> <@U020J2...

# openlane

Matt Venn

11/04/2022, 4:30 PM

is there a way to specify a clock port as one wire in a bus? like io_in[0] ? @Matt Liberty @donn

Matt Venn

11/04/2022, 4:31 PM

image.png

Christof Gindu

11/04/2022, 4:32 PM

maybe with io_in\[0\] The tcl script messes up brackets

Mitch Bailey

11/04/2022, 4:54 PM

I think you mean

io_in\[0\]

. You could also try

{io_in[0]}

Christof Gindu

11/04/2022, 5:05 PM

Of course, thank you!

Matthew Guthaus

11/04/2022, 8:18 PM

Yes, we did this with openram_testchip. There was also a bug but I hope/think it got fixed in OpenLane. I filled an issue...

Matt Venn

11/06/2022, 5:00 PM

thank you

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