Is there a possibility to specify two clock ports in OpenLane? I'm integrating two digital blocks with individual clocks into one design.

I think you can use

set ::env(CLOCK_PORT) {clk1 clk2}
set ::env(CLOCK_NET) {clk1 clk2}

Thank you for the quick response but this didn't solve the problem. It seems that two ports might not be possible...

Update

.sdc

with

create_clock

for your requirement and use it in the flow. Refer following example defining two clocks with sdc file: https://github.com/egorxe/miranda_fpga_openmpw/blob/main/openlane/fpga_struct_block/fpga_struct_block.sdc

Thank you very much for your help! Is it enough to create and empty .sdc-file with the "create_clock" lines or do I have to add more information? (of course I included the .sdc-file in the config.tcl with "BASE_SDC_FILE")

Update for both clock net with required delay information and use your current path for

set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/name.sdc

to avoid flow not to use default sdc file