Hi, we got 2 antenna violations after running openlane. We cannot find where violation in the report which is attached. Could someone please let us know how we might open the report and debug it? Thanks!
That's probably close enough that it won't be a problem, but I don't know how to waive them.
j
Jake Ke
06/18/2022, 1:15 AM
Thank you, @Mitch Bailey! We do not understand why we have antenna errors for those ports. They are not the longest nets either. For a design with the same pin assignments and floorplan, by just changing period, we could have antenna errors on different ports.
m
Mitch Bailey
06/18/2022, 1:21 AM
Look at the ratio of gate area to the total connected licon, met1, met2, and met3 area. Increasing the input gate size might help.
c
Chris Michael Calloway
06/18/2022, 1:28 AM
Hi Mitch, I am Jake's project partner. How would we go about increasing the gate size? By specifying a larger fan-out?
m
Mitch Bailey
06/18/2022, 1:35 AM
Hey Chris. Sorry, I have no clue, but a larger fan-out might work.
j
jeffdi
06/18/2022, 8:29 PM
@Jake Ke you can pretty much ignore antenna violations as they should only affect yield. they do not block tapeout submissions.
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