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<@U019TF3364X> was it you asking about the debug vexrisc? I can't remember.

• Anyway, here's Jeff's answer: yes - what was implemented is a debug UART that is connected directly the wishbone bus as a master.  the uart port on the chip is muxed between the debug uart and the standard uart implement in the SoC.  It is selected based on the debug_in input (high for debug uart)  Here is a link to the testbench and the Lite code that implements this.  The block diagram needs to be updated.
• <https://github.com/efabless/caravel_mgmt_soc_litex/tree/main/verilog/dv/tests-standalone/debug>
<https://github.com/efabless/caravel_mgmt_soc_litex/blob/aac1f07f993507d6369b31ae68ca5a5d3b242301/litex/caravel.py#L225> (edited)

If I remember well it was <@U030T3T7672>  question.
Any case thanks for the info, It will be good  to use that uart to debug firmware when the chips came.

<@U0172QZ342D>  My question was :
when I run user_project_wrapper there are only slew checks. no timing paths are identified, so there aren't any hold or setup sta checks.
looks like openlane is not generating a liberty view of the instanciated design. This could be critical for hierarchical flow, where a design need to be breakdown into multiple macros  (due to memory or runtime issues). If there are no sta checks on paths between macros, there could be hold or setup violations.

I saw that current mgmt_core config.tcl incl have the following for srams :
set ::env(EXTRA_LIBS) "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib"

Is there any variable to set opelane to generate liberty of the hardened macro?

Ah yes, still waiting on <@U01634FH82K> to answer that

<@U0172QZ342D> looking at your latest interview, seems that this hierarchical sta was a serious problem xD