I'm trying to learn how to work with OpenLane and I'm trying to run this example on OpenLane, but I have several issues: I made these changes in the config.tcl: set ::env(PL_TARGET_DENSITY) "0.7" set ::env(FP_CORE_UTIL) "70" set ::env(PL_RANDOM_GLB_PLACEMENT) "1" set ::env(PL_RANDOM_INITIAL_PLACEMENT) "1" But I received this error: [ERROR PDN-0108] Spacing (1.1200 um) specified for layer met5 is less than minimum spacing (1.6000 um). Error: pdn_cfg.tcl, 129 PDN-0108 How can I fix it?

file a github issue here https://github.com/The-OpenROAD-Project/OpenLane/issues with

openlane_issue_reproducible

generated during runtime

Your basic placement config suggests that your chil area is small. Try setting the spacing for power grid manually or increasing the die area

set ::env(PL_TARGET_DENSITY) "0.7" set ::env(FP_CORE_UTIL) "70" set ::env(PL_RANDOM_GLB_PLACEMENT) "1" set ::env(PL_RANDOM_INITIAL_PLACEMENT) "1" Remove all above and run with default setting

If I remove these I get this error: [ERROR GPL-0302] Use a higher -density or re-floorplan with a larger core area. Given target density: 0.55 Suggested target density: 0.61 Error: replace.tcl, 91 GPL-0302 child process exited abnormally

That means PDN error resolved now

But I need to make the density bigger. when I put it 0.7 I receive the error I mentioned.

Don't use CORE_UTIL. Just set density to 0.7 and run the flow

Now, I have another error: [ERROR]: during executing openroad script /openlane/scripts/openroad/resizer.tcl [ERROR]: Exit code: 1 [ERROR]: full log: designs/Universal_shift_register/runs/mod_conf_1/logs/placement/8-resizer.log [ERROR]: Last 10 lines: [INFO DPL-0035] 47 [INFO DPL-0035] 36 [INFO DPL-0035] 36 [INFO DPL-0035] 36 [INFO DPL-0035] repeater15 [INFO DPL-0035] input6 [INFO DPL-0035] input6 [ERROR DPL-0036] Detailed placement failed. Error: resizer.tcl, 79 DPL-0036 child process exited abnormally

set ::env(FP_CORE_UTIL) "40"

same error

can you share

runs/tag/config.tcl

?

config.tcl

Still

set ::env(FP_CORE_UTIL) {50}

shows same. I told to try with 40

New error in generating PDN: [ERROR]: during executing openroad script /openlane/scripts/openroad/pdn.tcl [ERROR]: Exit code: 1 [ERROR]: full log: designs/Universal_shift_register/runs/mod_conf_1/logs/floorplan/6-pdn.log [ERROR]: Last 10 lines: [INFO ODB-0226] Finished LEF file: /openlane/designs/Universal_shift_register/runs/mod_conf_1/tmp/merged.unpadded.nom.lef [INFO ODB-0127] Reading DEF file: /openlane/designs/Universal_shift_register/runs/mod_conf_1/results/floorplan/Universal_shift_reg.def [INFO ODB-0128] Design: Universal_shift_reg [INFO ODB-0130] Created 13 pins. [INFO ODB-0131] Created 73 components and 424 component-terminals. [INFO ODB-0133] Created 47 nets and 158 connections. [INFO ODB-0134] Finished DEF file: /openlane/designs/Universal_shift_register/runs/mod_conf_1/results/floorplan/Universal_shift_reg.def [ERROR PDN-0191] Offset of 3.9680 does not fit the manufacturing grid of 0.0050. Error: pdn_cfg.tcl, 129 PDN-0191 child process exited abnormally

universal_shift_reg is your design right?

No, I am just trying to run an example to learn OpenLane.

https://github.com/The-OpenROAD-Project/OpenLane/tree/master/designs/spm have you understood these built-in examples?

More or less, but we can change the configurations by changing config.tcl, right?

yes. For your design try below setup

# User config
set ::env(DESIGN_NAME) Universal_shift_reg

# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]

# Fill this
set ::env(CLOCK_PERIOD) "10.0"
set ::env(CLOCK_PORT) "clk"
set ::env(PL_TARGET_DENSITY) "0.7"
set ::env(CELL_PAD) 1
set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
	source $filename
}

It is running, but I didn't understand why? because based on this: The only value to consider here is the

CELL_PAD

which is usually selected for each (PDK,STD_CELL_LIBRARY) and should mostly be left as is. However, typically for the skywater libraries the value should be 4~6.

There are many configuration available to tweak to complete design from RTL to GDSII. So based on your requirement, you're free to change

based on this: Cell padding; increases the width of cells.

what CORE_UTIL will do? you're given 70. For tiny designs you should follow certain guidelines to complete automated flow.

Well, in the first error with the default config values, It suggested changing core area: [ERROR GPL-0302] Use a higher -density or re-floorplan with a larger core area. Given target density: 0.55 Suggested target density: 0.61 and based on this: • If your design is not a tiny design, then

PL_TARGET_DENSITY

should have a value that is

FP_CORE_UTIL

+ 1~5%. Note that

FP_CORE_UTIL

has a value from 0 to 100, while

PL_TARGET_DENSITY

has a value from 0 to 1.0. I thought that since I need to increase density, I need to increase FP_CORE_UTIL too. FP_CORE_UTIL is The core utilization percentage. (Which I don't understand it)

https://github.com/The-OpenROAD-Project/OpenLane/blob/master/designs/spm/config.tcl https://github.com/The-OpenROAD-Project/OpenLane/blob/master/designs/spm/sky130A_sky130_fd_sc_hd_config.tcl Do an iteration with this value and learn it. why/where/how it fails and how to fix it. Same design can be able to complete with different values

Thank you so much, @Vijayan Krishnan . You were a great help. I will try the example and learn from it.