Hi @Stefan Schippers - i am doing bussed instantiation as below. In spice , the inst is being output as below : x3_WL<15:0> IN1_WL<15:0> IN0_WL<15:0> OUT_WL VDD VSS V1_WL<15:0> V2_WL<15:0> V3_WL<15:0> V4_WL<15:0> + pmos_switch Is this valid spice syntax ? Also is there any way to split the busses to have individual inst , rather thab bussed ? Thanks