hi @Tim Edwards , two queries regarding LEF generation : 1. How are the shapes for the PINS determined in lef write command ? 2. I see although i have created the pin over met1 , VDD/VSS pins have RECT shapes for other layers as well Also any recommended settings for writing LEF file -- for using it on openlane of any higher flow ? Thanks.

For a small layout like a standard cell, use

lef write

. For a large macro, use

lef write -hide

so that it just blocks the whole area (except the pins) with obstruction. The pins are determined by enumerating all shapes on a net and making all of them into shapes in the PIN record. There are various options to the

lef write

command for limiting the area marked as a pin. I expect what you want is just to do

lef write -hide

. Without

-hide

, all the internal nets will be in the abstract view; if the nets connect to a pin they will be part of the pin, and if not, they will be marked as obstruction layers.

@Tim Edwards A related query here is that in klayout i see there are PIN layers also. Ideally , if we create layers on the PIN layer , that only should be extracted in the LEF file - Is this understanding true ? This helps also to seperate the drawing layer and interface pin layer. But i dont see these PIN layers in magic . Am i missing anything here ?? Thanks

Does klayout read LEF files? If so, is it giving you any relevant error message? The problem with the purpose might be that you need both the pin and drawing purposes; a pin purpose layer by itself is not legal layout.

This error message is being displayed. What i have noticed is that when there is a particular syntax issue (klayout related may be but not generic) , klayout throws this error.

In magic you need to follow that by

load <cellname>

, presumably here

load decoder_with_pmos_D1_g5d10_tapped_2305

.