@User the trailing _1, _2, ... is just the driver strength of the standard cell. A

_2

cell is driving the output with a ~2x buffer size compared to

_1

cell. In general i believe dl* are d type latches, level triggered, df* are d-type flip flops, that is, clock edge triggered.

Thank you! Is there somewhere a schematic of how they are build with individual transistor size?

@Faedra Webers I don't know if there are schematics of the standard cell implementations. I got one simple implementation (a mux2 iirc) by reverse engineering the netlist, but that work is not funny at all. May be @Tim Edwards knows if there are some images / schematics of the stdcell transistor implementations.

@Faedra Webers: Sadly, no, we don't have schematics of the standard cells, only SPICE netlists.