Hi , Have a query regarding LVS... My comp.out in netgen is having below output. Seems all the mismatch nets are due to the substrate naming. I connected the substrates for the layout at the top level and for the schematics , its done in the basic gates too. Any idea why its failing ? Subcircuit summary: Circuit 1: decoder_4x2_g5D10 |Circuit 2: decoder_D1_g5d10 -------------------------------------------|------------------------------------------- sky130_fd_pr__pfet_g5v0d10v5 (14) |sky130_fd_pr__pfet_g5v0d10v5 (14) sky130_fd_pr__nfet_g5v0d10v5 (14) |sky130_fd_pr__nfet_g5v0d10v5 (14) Number of devices: 28 |Number of devices: 28 Number of nets: 18 Mismatch |Number of nets: 28 Mismatch --------------------------------------------------------------------------------------- NET mismatches: Class fragments follow (with fanout counts): Circuit 1: decoder_4x2_g5D10 |Circuit 2: decoder_D1_g5d10 --------------------------------------------------------------------------------------- Net: VSS |Net: VSS sky130_fd_pr__nfet_g5v0d10v5/3 = 10 | sky130_fd_pr__nfet_g5v0d10v5/3 = 10 sky130_fd_pr__nfet_g5v0d10v5/4 = 14 | | (no matching net) |Net: /and2_g5D10_1//nand_D1_g5d10_0/VSUBS | sky130_fd_pr__nfet_g5v0d10v5/4 = 2 | (no matching net) |Net: /and2_g5D10_2//nand_D1_g5d10_0/VSUBS | sky130_fd_pr__nfet_g5v0d10v5/4 = 2 | (no matching net) |Net: /and2_g5D10_3//nand_D1_g5d10_0/VSUBS | sky130_fd_pr__nfet_g5v0d10v5/4 = 2 | (no matching net) |Net: /and2_g5D10_0//nand_D1_g5d10_0/VSUBS | sky130_fd_pr__nfet_g5v0d10v5/4 = 2 | (no matching net) |Net: /and2_g5D10_0/VSUBS | sky130_fd_pr__nfet_g5v0d10v5/4 = 1 | (no matching net) |Net: /and2_g5D10_1/VSUBS | sky130_fd_pr__nfet_g5v0d10v5/4 = 1 | (no matching net) |Net: /and2_g5D10_2/VSUBS | sky130_fd_pr__nfet_g5v0d10v5/4 = 1 | (no matching net) |Net: /and2_g5D10_3/VSUBS | sky130_fd_pr__nfet_g5v0d10v5/4 = 1 --------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------- Net: IN1 |Net: IN1 sky130_fd_pr__pfet_g5v0d10v5/2 = 3 | sky130_fd_pr__pfet_g5v0d10v5/2 = 3 sky130_fd_pr__nfet_g5v0d10v5/2 = 3 | sky130_fd_pr__nfet_g5v0d10v5/2 = 3 | Net: IN0 |Net: IN0 sky130_fd_pr__pfet_g5v0d10v5/2 = 3 | sky130_fd_pr__pfet_g5v0d10v5/2 = 3 sky130_fd_pr__nfet_g5v0d10v5/2 = 3 | sky130_fd_pr__nfet_g5v0d10v5/2 = 3 | Net: IN1_inv |Net: inverter_d5g10_W1um_L0p420_1/OUT sky130_fd_pr__pfet_g5v0d10v5/2 = 2 | sky130_fd_pr__nfet_g5v0d10v5/2 = 2 sky130_fd_pr__nfet_g5v0d10v5/2 = 2 | sky130_fd_pr__pfet_g5v0d10v5/2 = 2 sky130_fd_pr__pfet_g5v0d10v5/1 = 1 | sky130_fd_pr__pfet_g5v0d10v5/1 = 1 sky130_fd_pr__nfet_g5v0d10v5/1 = 1 | sky130_fd_pr__nfet_g5v0d10v5/1 = 1 | Net: IN0_inv |Net: inverter_d5g10_W1um_L0p420_0/OUT sky130_fd_pr__pfet_g5v0d10v5/2 = 2 | sky130_fd_pr__nfet_g5v0d10v5/2 = 2 sky130_fd_pr__nfet_g5v0d10v5/2 = 2 | sky130_fd_pr__pfet_g5v0d10v5/2 = 2 sky130_fd_pr__pfet_g5v0d10v5/1 = 1 | sky130_fd_pr__pfet_g5v0d10v5/1 = 1 sky130_fd_pr__nfet_g5v0d10v5/1 = 1 | sky130_fd_pr__nfet_g5v0d10v5/1 = 1 --------------------------------------------------------------------------------------- Netlists do not match. Netlists do not match.

That's a substrate issue. Circuit 1 has all device bulk terminals (4th terminal) tied to VSS. Circuit 2 has them all isolated. That suggests that your layout has no substrate taps?

@Ryan R Could you post your netlists and the command used to run LVS? @Tim Edwards You're assuming Circuit 2 is the layout, correct?

@Mitch Bailey: Yes, the output appears to indicate that the netlists were passed in the order (schematic, layout).

@Mitch Bailey attached

What version of magic are you using?

Magic 8.3 revision 266 - Compiled on Thursday 10 February 2022 111028 PM IST.

There were some changes to the substrate extraction. Can you use a later version (maybe after 8.3.274) and see if you get the same results?

ok i will update the magic to latest version and check once