For anyone struggling with getting the reram model to work in xyce, if you have access to Hspice or Spectre, you can use the hspice model I created from the ngspice models. The hspice model is available at https://github.com/lekez2005/open_pdks/releases. Just download and extract the hspice-models.tar.bz2. Hspice/Spectre can correctly (at least qualitatively) simulate switching and read behaviors modeled in the Verilog-A model

@User ^

hi @User which one is the spice file - there are a lot of files but none seems to have the reram

The reram model is based on Verilog-A and is available at https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram, specifically https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram/blob/main/cells/reram_cell/sky130_fd_pr_reram__reram_cell.va. Since it's Verilog-A based, it can be simulated using Hspice (and supposedly Xyce). The models I linked to above enable simulating the Sky130 TRANSISTOR models in Hspice (default Sky130 models don't work in Hspice) which means you can now co-simulate reram+transistor models in Hspice.

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