We have 5 projects packaged and undergoing bring-up testing for the management core in Caravel. Unfortunately, those tested projects have revealed a timing issue with the clock tree for Caravel management core resulting in multiple hold violations.  We have run through an exhaustive set of bench tests and simulation studies including a range of operating voltages and frequencies and other conditions across 20+ boards.  While we have been able to run limited software routines on the management core for some boards under specific operating voltages, we have not been able to successfully configure the user IO on Caravel to enable a project to operate.  We believe there is a timing violation with the clock tree that is preventing user IO configuration to complete successfully.

No worries, this is the beauty of open-source community, things need time to get stable and we always learn from our mistakes. Good Job everyone and Congratulations ALL!

@jeffdi I believe my chip should survive. I was not connected to the clock.