I guess you've already tried running at very slow ...
# mpw-one-siliconm
Matt Venn
10/02/2021, 9:12 AMI guess you've already tried running at very slow clock?
t
tnt
10/02/2021, 9:19 AMUnfortunately for hold violations, a slow clock doesn't help. You need to slow down the propagation time, which I guess is why they're running it at 1.26v which is way under the 1.8v nominal to try and slow down the fabric.
tnt
10/02/2021, 9:20 AM(just a guess though)
m
Matt Venn
10/02/2021, 9:37 AMimage.png
👀 1
Matt Venn
10/02/2021, 9:38 AMwouldn't making a longer period give the data longer to settle, solving both setup and hold?
t
tnt
10/02/2021, 9:51 AMNo.
(1) that graphic is terrible ...
tnt
10/02/2021, 9:51 AM(2) Hold violation are relative to a single clock edge.
tnt
10/02/2021, 9:52 AMSo it's basically the clock to out of the previous FF being too fast and the output changes too soon after the clock edge and that violates the hold requirement of the next FF in the chain, but on the same clock edge.
tnt
10/02/2021, 9:53 AM(either it's too fast or there is skew in the time the clock distribution causing it to toggle too soon ... same effect)
k
Kunal
10/02/2021, 10:12 AM@Matt Venn hold is single cycle check, so it doesn't matter what is clock period
t
Tim Edwards
10/02/2021, 2:38 PMYes, the clock can be slowed down to practically zero and the behaviors remain the same. What does affect hold violation timing is voltage, temperature, and the statistical spread of parameters across the wafer. So some of the issues that are due to very marginal hold timing can be overcome by dropping the voltage from 1.8V down to, say, 1.5V. I tried blasting it with a hot air gun but didn't get much effect from that. Different samples of the chips from different spots on the wafer exhibit different behavior, because a lot of the hold timing violations are marginal.