is there a way to see the clock tree in caravel? like extract the whole thing and look at it in klayout?

Yes: "KLayout Layout Viewer And Editor" https://www.klayout.de/doc-qt5/manual/net_tracing.html

That's what I was thinking

The clock wires get random names in the Verilog IIRC and these won't really be in the layout. There could probably be a script that highlights multiple nets using the trace feature and iterating from input to output of buffers

I haven't even looked at all the files produced by the cts program. Maybe there's a list of coordinate there

CTS uses regular names for the clock buffers and nets. clknet* for nets and clkbuf* for instances

I swear I saw random names when I was debugging clock nets in openlane, but I look at my final design now and they are regularly named.

@Matt Venn I guess you could write custom script that expand a selected net with nets on the output of a certain buffer on that.

I'm gonna learn how the openroad GUI works, looks pretty useful

I'm very late to the party but you can select the nets in KLayout by opening the routing .def file, Edit -> Search and enter a custom search string

shapes from instances of ... where shape.property(1) ~ "{clk,clknet_*}"

Select all the shapes -> Export to Layout. Then you can open the final GDS and "File -> Pull in other layout -> query_results" to overlay the clock tree.