Did I read that timing report right that the clock skew is like 10 ns ?

Where did you see the report?

@tnt: Yes, you read that right. If you trace through the clock tree in verilog/gl/mgmt_soc.v, you'll find that the root of the so-called "tree" has a fanout of 924 cells. The root node is clocking some flops, and then other flops are clocked after a chain of six or seven buffers. The slew of that heavily loaded root node is close to 2ns. The difference in arrival time between the root node and the ends is something like 12ns.

Hi @User There must be common clock path (report_timing -path_type full_clock_expanded), where some pessimism can be removed. Is there a way to enable CPPR? That way we would know exact amount of hold violation that needs to be fixed

You're talking to the wrong person. I didn't have anything to do with the digital synthesis of the Caravel core.