I'm curious, has anyone else tried or planning to try bringing up the chip ? There were quite a few analog designs too IIRC and also some digital designs that were not made with openlane.

The main issue is that without being able to control the state of the GPIO, there's not much hope of communicating with what's inside the user project area, whether it's analog or digital. You gave me hope that there are some chips out there that can get the GPIO configured. But it's a tricky process, regardless.

Do even analog project need the IO configured ?

I guess in the default configuration the only concern would be that the input buffer is active and any mid-range analog voltage could cause the digital input buffer to crowbar. But that wouldn't necessarily interfere with anything.

Ah yeah, good point. Filling the shift reg with 1 is pretty easy though and should disable input/output buffer I think. It's hard to predict where bits end up for a good config, but blanket fill should be easy enough.

True, and it should work as long as the configuration process will count correctly and trigger the load correctly (which mine never did).