********************************************* <!channel> Hello everyone, We just posted a campaign for a demo board called CLEAR with an updated version of Caravel and an open eFPGA implementation.  Whether you have already done a project on a shuttle, or you are planning one in the future, this is great opportunity to get a working instance of the Caravel chip to test drive the hardware.  It’s also a good example of what can be implemented with an eFPGA using the OpenFPGA generator framework.

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That's awesome! I didn't realize it was based on the caravel. That sounds like great way to validate shuttle digital design on real hardware.

Cool

Is it 8x8 CLB Means? As per OpenFPGA document , Each CLB Made of 4 BLE and Each BLE has 4 input LUT (Look up Table) and a FF and 2:1 Routing Mux 8x8 CLB means 8x8x4 = 256 FF 8x8x4 = 256 LUT 8x8x4 = 256 Mux Look to be too small digital logic only can fit in this FPGA ?