Hi @User @User @User We are at LVS for our full chip and running into issues: The generated spice file for all the RAMs are missing pins for VPWR and VGND. according to LEF, we have VPWR, several VPWR.extra*, VGND, and several VGND.extra*. The spice file only lists a single VPWR.extra and VGND.extra. Similarly, the powered gate level netlist only lists VPWR and VGND.

can you provide your lvs report, your spice extraction tcl script and you netgen command invocation ?

We aren't doing LVS at the RAM level, this is at the project level. Our project is very big, so it may not make sense to look at our reports. You actually don't even have to run netgen to see the issue. There's a mismatch in the ports between the lef file and the gate level powered netlist and the spice