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```.options nonlin continuation=gmin .options time...
# xyce
c
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.options nonlin continuation=gmin
.options timeint method=trap
.options device temp=25
**.options output initial_interval=1e-8 # DONOT USE THIS SEEMS TO GO CRAZY EVEN WITH INPUT SIGNAL
.options parser model_binning=True
.options parser scale=1e-6
**** Oscillator specific options
.options timeint newlte=0
.options timeint erroption=1 delmax=1.0e-12

* Model Includes and Std Cell Includes

.param mc_mm_switch=0
.param mc_pr_switch=0
.lib ../../PDK/open_pdks/sky130/sky130A/libs.tech/ngspice/sky130.lib.spice ss
**.include "../../PDK//open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd_Xyce.cdl"
.include ../../PDK/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
.include ../../PDK/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_hs/spice/sky130_fd_sc_hs.spice
.include ../../PDK/open_pdks/sky130/sky130A/libs.ref/sky130_fd_sc_ms/spice/sky130_fd_sc_ms.spice
.include ../../PDK/open_pdks/sky130/sky130A/libs.tech/ngspice/sky130_fd_pr__model__inductors.model.spice
*.include ../../PDK/open_pdks/sky130/sky130A/libs.tech/ngspice/capacitors/sky130_fd_pr__model__cap_mim.model.spice


** LC Core
.subckt LC_Cell Ibias outn outp ind_sub VDD GND
*.ipin Ibias
*.opin outn
*.opin outp
XM1 outp outn net2 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=10
XM2 outn outp net1 GND sky130_fd_pr__nfet_01v8 L=0.15 W=1 nf=10
XM3 net2 Ibias GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=4.8 nf=10
XL1 outp outn VDD ind_sub sky130_fd_pr__ind_05_220
XC1 outp outn sky130_fd_pr__cap_mim_m3_1 W=1 L=1 MF=2056 m=1
XM4 net1 Ibias GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=4.8 nf=10
XM5 Ibias Ibias GND GND sky130_fd_pr__nfet_01v8 L=0.15 W=4.8 nf=5
.ends

.param pvdd = 1.8
.param bias = 1.0
.param Icurr = 30u

* --- Voltage Sources ---
**vvdd VDD 0 dc 'pvdd'
vvss GND 0 dc 0
vsig VDD 0 pwl(0 0 10n 0 20n 'pvdd')
*vtail tail_v 0 dc 'bias'
Idctail VDD tail_c 'Icurr'
* ---LCCell Subcircuit------
xlccore tail_c outp outn open VDD GND LC_Cell


** LC Circuit **
**.dcvolt v(outn)='pvdd/2'
**.dcvolt v(outp)='0'
*.ic v(tail)=1.6

* --- Transient Analysis ---
.op
*.dc vtail 0.4 1.4 0.01
**.dc Icurr 10u 11u 0.1u
.tran 0.01p 100n
* --- Measurement ---
*.print DC v(*)
.print tran v(outp)
.print tran v(outn)
.print tran v(*)
.print tran i(*)
.print tran v(VDD)
.print tran ID(XLCCORE:XM1:MSKY130_FD_PR__NFET_01V8)
.print tran ID(XLCCORE:XM2:MSKY130_FD_PR__NFET_01V8)
.print tran ID(XLCCORE:XM3:MSKY130_FD_PR__NFET_01V8)

.end
r
Oscillating circuits aren't going to have great numerical stability in terms of finding a quiescent point. You'll want to add 
NOOP
to your 
.tran
line to prevent the DC OP point calculation from running. Just make sure your ICs aren't non-physical, and you should be good to go. Actually I think Xyce defaults to setting all voltage nodes to zero if DC OP is skipped, which should be fine in your case, but might introduce some high-order modes to the transient behavior at the start of the sim.
c
Thanks for the quick reply I will run and report back!!
Hey noop fixed the issues, thanks I am able to see startup!! Thanks a lot
Hey I switched out the device from RVT to LVT and I am suddenly seeing
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Netlist warning: Excessively small current time step, incorrectly returning
 with large value
Any ideas to what might be causing these?
e
Sorry I didn’t reply right away. The entire Xyce team has been off for the holidays. Anyway, I agree with Robert’s comment that oscillating circuits often don’t have stable operating points. Even if the DCOP calculation converges, you probably don’t want to bother with it.
Robert is correct that if you use 
NOOP
or 
UIC
on the tran line, the DCOP operating point calculation is skipped, and by default everything is set to zero. For some oscillators, they will only oscillate if one of the nodes is set to a nonzero value via .IC. When combined with 
NOOP
or 
UIC
, the DCOP is still skipped, but the 
.IC
statement will apply that as an initial condition. If your circuit oscillated without it, no need to bother with it, but you might keep that in mind for other oscillator circuits.
The warning message you report means that your time step has gotten smaller than 1e-30 seconds. When that happens, various numerical problems can happen due to roundoff errors. The Jacobian matrix can become very poorly conditioned, as capacitive terms will appear in the matrix as 
(alpha*C/dt)
entries, where alpha is the leading term of the time integration formula. When dt is this small, it can lead to a style of failure we often call the “capacitive spiral of death”. The matrix solve becomes unreliable, which leads to a time step failure, which leads to Xyce cutting the step, which just makes the problem worse. Xyce attempts to mitigate this issue in the Jacobian, by scaling the 
(alpha*C/dt)
Jacobian entries when the time step is this small. The warning message was letting you know that Xyce is doing this. If your circuit is running all the way thru and giving you a reasonable answer I wouldn’t worry about this warning.
c
@User the circuit is not working properly and the transient simulation fails after. No node voltages are updated.
Actually the step is as low as 10e-300 !! I will try and vary the IC on some nodes but not sure if that alone is the cause.
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Netlist warning: Excessively small current time step, incorrectly returning
 with large value
 *** Transient failure history:
Time        Time      Step      Non-Linear Solver      node    node
(sec)       Step     Status   Status   Iters   ||F||   index   name
 0.000e+00  1.026e-301  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  1.283e-302  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  1.603e-303  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  2.004e-304  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  2.505e-305  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  3.132e-306  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  3.914e-307  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  4.893e-308  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  6.116e-309  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  7.645e-310  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  9.557e-311  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  1.195e-311  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  1.493e-312  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  1.867e-313  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  2.333e-314  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  2.916e-315  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  3.646e-316  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  4.557e-317  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  5.696e-318  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  7.120e-319  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  8.900e-320  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  1.113e-320  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  1.393e-321  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  1.729e-322  fail  F:NaN     1  0.000e+00     -1    N/A
 0.000e+00  1.976e-323  fail  F:NaN     1  0.000e+00     -1    N/A
Time step too small near step number: 0  Exiting transient loop.

***** Solution Summary *****
        Number Successful Steps Taken:          0
        Number Failed Steps Attempted:          345
        Number Jacobians Evaluated:             345
        Number Linear Solves:                   345
        Number Failed Linear Solves:            0
        Number Residual Evaluations:            690
        Number Nonlinear Convergence Failures:  345
        Total Residual Load Time:               0.006 seconds
        Total Jacobian Load Time:               0.001 seconds
        Total Linear Solution Time:             0.002 seconds
@User I cant seem to get past the LC oscillator beyond a basic LC (i.e when I add switches to control the cap). I have tried setting some of the nodes with .IC but this approach doesn't seem working or scalable ? Are there any beta features that will enable debug on this front ? I can provide my setup if this needs to be taken. I did go through the chapter on initial conditions and couldnt see anything that will help. I have cycled through LTE options as well.
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