@User I am open to this. Can you send me more info about it?

That's about the whole description. I have code in the ngspice repository under

src/xspice/icm/digital/d_genlut

. If you could point me to where the digital behavioral models are implemented in the Xyce source, I might be able to do the implementation myself and just send you a pull request.

Yes, that is the file containing the digital devices. You have found them. They haven’t always been numerically well-behaved, is probably my main concern about them. But possibly this is an opportunity to revisit that issue. I’ll take a look at

src/xspice/icm/digital/d_genlut

as well.

The only thing I'm not sure about is whether I can implement an arbitrary number of outputs. Since I have never seen a standard cell set with gates with other than either one or two outputs, I could always just implement a one-output LUT model and a two-output LUT model. I guess I'm also not sure whether it is valid to set the number of inputs to zero, as would be needed for a tie-high or tie-low cell.

@User I know standard cells that have two logical outputs and provide them both positive and inverted, so that would make 4 outputs from a single cell. Well, and there are full adders....

@User: The full adder is already in the set implemented in Xyce. But yes, even the sky130 standard cells have the "conb" cell, which is a 0-input, 2-output cell (and is a non-standard, royal pain that kept breaking all the tools, but that's another matter). So I would probably opt for two LUT cells, one with one output and one with two outputs, unless it turns out that implementing

U<name> <type>(<num inputs>)(<num outputs>)

is easy, which it might be.

@User today is pretty busy for me, but I’ll try to take a look.

@User: If you know of a link where I could find a reference to a working digital example netlist, that would probably be all I need.

The main thing I’d suggest is the digital tests in our regression suite. The directory path is: Xyce_Regression/Netlists/DIGITAL And you can see them here: https://github.com/Xyce/Xyce_Regression/tree/master/Netlists/DIGITAL

Great, that's perfect.

I will comment that I’ve never been that happy with the robustness of the digital models in Xyce. They were intended (years ago) to mimic a similar feature in Pspice. But they haven’t ever worked as well as I would like them to. A lot of people just link Xyce to a digital tool (like icarus verilog) and do mixed signal simulation that way.

The issue with the digital was just that the parameter defaults for

S0RLO S0RHI S1RLO S1RHI

are unrealistic and need to be set before the simulation will produce any change in the output. I have also been looking at the mixed-signal API. It is very similar to the implementation for ngspice, although the ngspice implementation always had the drawback that the maximum timestep had to be kept very low or else the digital transitions would get missed. If I'm not mistaken, both implementations are build around the VPI interface which implies that Xyce or ngspice is launched from the verilog simulator, which then limits the verilog to a single process. Probably a sufficiently clever script could generate a wrapper verilog module incorporating multiple modules to be simulated as verilog, and figure out all the connections into and out of the SPICE netlist. Anyway, I do intend to play around with the mixed-signal simulation in Xyce sometime soon. But I like the embedded digital simulation capability, because I can use a simple script to convert any digitally-synthesized subcircuit into its digital component equivalent, and swap it in for the original with an

.include

statement. Sure, it takes longer to run than cosimulation, but the embedded digital simulation requires zero effort if you have the script to convert the analog subcircuits to digital (which I do, for ngspice, and can do a quick rewrite for Xyce once I've implemented the LUT model).

Hi @User, glad to hear you got it working!

Understood.