Hello everyone. Just wanted to get confirmation if you have received this notice as well as any status update. To confirm, the following projects we identified as being potentially impacted by this issue…

caravel-hs32core, caravel_astria_testchip, caravel_pyfive, caravel-mph, caravel_amsat_txrx_ic, Caravel-SOFA-HD, caravel_OpenTDC, caravel_skywater130_decr, caravel_aes, Caravel-OpenFPGA-EF, caravel_fpga250, Caravel-QLSOFA-HD, G_Skywater130nm_1stTO, Caravel-SOFA-CHD, caravel_riscv_osu

yes I am working on it

@jeffdi Just rechecked ( for caravel_pyfive ) and all

met5

present in the design are intended to be there and they connect to where I intend them to.

Hi @jeffdi, yes I confirm I had received the notice and had rehardened the macro according to the recommended steps, and now met5 is no longer seen in the macro. I have pushed the changes to the repo, but I might still need to re-check for issues.

Thanks @Astria Nur Irfansyah - let me know when you are good for me to pull and rerun

Thank you @jeffdi . I have only checked the following file

user_project_wrapper/runs/user_project_wrapper/logs/magic/magic_ext2spice.feedback.txt

. It is indeed empty. I have just run the open_mpw_precheck again, which I have just started using efabless, showing 71 DRC errors. Is this (still) expected?

@Astria Nur Irfansyah: Yes this is the expected count. We'll integrate it into the latest version and let you know if we see any new issues. Thanks!

@Astria Nur Irfansyah can you confirm your latest changes are update on your repo?

Dear Jeffdi @jeffdi, sorry for the late response, yes I confirm the latest changes are on the repo and had been on the repo when you asked. Many thanks.

thx. your project is all set.