Hi, With the tools available, what is the recommendation for post-layout simulations focusing on the digital performance of user area? The design has been fully simulated with iverilog. I am interested to simulate the “final” results and look at expected timing/performance.

In general, you verify a design with static timing analysis. I have always done a dynamic simulation of the gate level with SDF annotation of delays as well. For specifics of openlane, you would want to ask there.

Thanks

I think @Tim Edwards said IRSim could be used for that kind of simulation. AFAIK none of the open source verilog simulators support SDF annotations.