@User typically, you compare the schematic netlist which is created by the designer as spice or a structural verilog file from synthesis with an extracted netlist from the layout. This ensures that the layout correctly represents the initial netlist. This gets complicated with physical synthesis though if you change sizes during layout, add buffers, etc.

so sir the extracted netlist have parasitics too right,, does the lvs tool neglect parasitics while doing lvs, especially(netgen)

You can just extract the devices and connectivity without parasitics.

oh ok great,thanks