can someone explain me use of FLASH_IO0,FLASH_IO1,...
# vlsi101v
Varun Majji
04/15/2021, 12:04 PMcan someone explain me use of FLASH_IO0,FLASH_IO1,FLASH_IO2 pins in spiflash
m
Matt Venn
04/15/2021, 1:25 PMthose are the data lines for the flash chip. The firmware for the picorv32 lives on the flash
Matt Venn
04/15/2021, 1:27 PMin single line data mode, only one is used, but this flash controller supports QSPI so 4 times the data can be read in 1 clock cycle
Matt Venn
04/15/2021, 1:27 PMimage.png
Matt Venn
04/15/2021, 1:27 PMv
Varun Majji
04/15/2021, 1:48 PMthanks a lot
t
Tim Edwards
04/15/2021, 2:44 PM@Varun Majji, @Matt Venn: FYI, the caravel chip on MPW-one only used IO0 and IO1 and so only supports slow mode. A few days ago I pushed an update to the Caravel design for MPW-two that adds IO2 and IO3 as optional I/O that can be used to run in QSPI mode. (Also note DDR mode, which drives data on both clock edges, which can get 8 times the data per clock cycle).
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Varun Majji
04/18/2021, 3:11 PMso sir its basicall noramal MISO and MOSI spi flash right which is currently being used
t
Tim Edwards
04/18/2021, 4:33 PM@Varun Majji: Yes, the default mode for the SPI flash chips is to run in the simple SPI mode where IO0 and IO1 map to MOSI and MISO, respectively, and that's what is supported by the version of Caravel on MPW-one. 2x mode will also run in this configuration, since it does not use IO2 and IO3.