Hi professor / All, Would like to understand how the read / write assist and read / write margin impacts the memory behaviour of SRAM . Please help to understand .

This is a large topic, so there are many aspects. What have you read so far?

Prof, When I change the read margin/ write margin , I see the post silicon results changes . In NOM mode, when read / write margin is faster , I see less bits failure, but when I keep read / write margin slow 2 mode I see more failures . So would like to correlate it, and what to understand how this impact our bit failures depending on voltage .