Ok, won't worry about it then. Another question. In wishbone the STB signal is used as a chip select, with device decode done outside the slave. Caravel doesn't seem to use it this way? Does the Caravel WB slave need to check the full 32 bit addrress for it's own range (say 'h3000000x)?

does it not? i was under the impression that

wb_intercon.v

generated all the stb signals https://github.com/efabless/caravel/blob/master/verilog/rtl/wb_intercon.v#L40

Yes, saw that. 6 slave ports are listed in the table. Note there is no entry for user project wb slaves.

Oh huh, I thought it was

mprj_stb_o

https://github.com/efabless/caravel/blob/master/verilog/rtl/mgmt_soc.v#L815 Actually, you can trace it through to caravel.v and it becomes

mprj_stb_o_core

then follow it through these inverting buffers https://github.com/efabless/caravel/blob/581068fea64d0d978f060a259cfbb2756bc88e90/verilog/rtl/mgmt_protect.v#L200 Unless I've been mistaken

Looks like any address not in that table, will pulse the user project's ws_stb line. Making it the user_project's slave's responsibilty to further decode the address if the user project requires more than one slave.