I included hardened design IP in user_project_example.gds and verilog instantiation in user_project_example.v What could be wrong, I am not able to get the IP inside caravel.gds

You need a

user_project_wrapper.gds

not a

user_proj_example.gds

.

And verilog instantiation, is it to be kept at user_proj_example.v or user_project_wrapper.v?

user_project_wrapper.v

should contain your design as well.

It is also not working. I had created the gds file of pll design outside openlane. And shows processing timestamp mismatches: user_project_wrapper.

Can you share your repo so I can take a look?