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Does anyone know where or how the user project area Wishbone bus Address gets selected? For example ...
# caravel
s
Does anyone know where or how the user project area Wishbone bus Address gets selected? For example I'm not seeing the 
0x3000_0000
address in here: https://github.com/efabless/caravel/blob/master/verilog/rtl/wb_intercon.v#L42-L49
m
@Steve Kelly These are the default values. They are overwritten from the top module by this https://github.com/efabless/caravel/blob/master/verilog/rtl/mgmt_soc.v#L267
s
Ah nice, thanks!
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