On another topic, if I want to run my code from RAM instead of flash - is this possible? We want to have a tiny tight loop that writes to the WB-bus without having to access the flash all the time. We've already tried things like adding a section to the .ld file, copying the code there etc. and not overwriting other stuff, but no luck so far.

@Matt Venn I am n't completely sure but I think you will also need the program counter to point to RAM address. Currently, it is hard coded in the mgmt_soc verilog to point to the flash base address https://github.com/efabless/caravel/blob/develop/verilog/rtl/mgmt_soc.v#L168 .

Thanks, that's good to know. My use case is to have a program in flash, but put certain functions in RAM, in order to make them run faster. So the initial loading and configuration can be done from flash the way it is already setup.

How slow is reading from flash?

@Matt Venn: I have been doing this a lot. If you look at the original source for picorv32 (and this is also in the caravel code, I think in the start.s assembly) there is a routine that reads the configuration registers from the flash. To do that, it has to load the routine in to RAM and then call it, because it cannot read the flash registers while simultaneously reading data off of the flash. But I have numerous routines that run in RAM using the same method of copying from flash and then calling the routine. The version in the picorv32 source is inefficient because it doesn't need to be efficient, so it copies the routine from flash every time. But that isn't necessary. My most complicated routine is an interrupt callback that reads data off of a PMOD MIC3 module. the MIC3 must be sampled at 32kHz, so the whole sampling loop must be very fast, so I have it run in RAM.

Great news. Coukd you post a link to the mic3 firmware pls?

@Matthew Guthaus (@Matt Venn): If you bump up to QSPI DDR mode with continuous read mode, you can get the flash to read at close to 4 bits per core clock cycle. The picorv32 is not pipelined, so I think the rate of reading from SRAM is 32 bits every 4 clock cycles, or 8 bits per core clock cycle, which means you can get the flash reads to be nearly 50% of what you could get on SRAM. But that's specific to the picorv32.

Thanks for the reply! Good to know that it is possible to run the flash that fast.