I still see caravel RTL using System version reserved syntax "*clocking*" in module instance definition

caravel/verilog/rtl/mgmt_core.v:	caravel_clocking clocking(

Due to this iverilog simulation with system verilog switch fails .. I have raised this issue in MPW-2 time also .. i still see the same issue .. Currently i am locally modifying it  ... This local change always give us issue in local pre-check run's (edited)