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# caravel
m
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t
That text is long outdated. In the most recent repository push, look at 
docs/postscript/memory_map.ps
. That has the correct sizes for the DFFRAM and SRAM. However, I am not entirely sure if the RAM addresses are correct for the VexRISC (@User, can you confirm?)
I am busy working on updated documentation. We decided to push everything for MPW-four knowing that some of the documentation was outdated. Sorry for the confusion.
m
the question I'm trying to ask is about shared SRAM, is that available in MPW4?
SRAM accessible from user project side
t
You're talking about a wishbone multi-master configuration. @User: Does the VexRISC allow a multi-master wishbone?
The dual-port SRAM's 2nd port is read-only; for now (including MPW-4) it faces the housekeeping system. I am particularly concerned that for diagnostic purposes I should be able to access RAM from outside the CPU. If all that seems to work right in the next batch of chips, I might move the 2nd port from housekeeping to the user project. However, it will still be read-only (unless, as I mentioned above, you have a multi-master wishbone).
m
from just talking with @User I think the readthedocs docs are outdated. So you can probably ignore everything I wrote.
j
@User @User it does but we did not configure a master from the user project area.
t
@User: That should be in the caravel issues as a to-do item for the following MPW.
j
yes
m
we've added it to our own MPW4 submission, if it's useful please feel free to reuse
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