https://open-source-silicon.dev
Join Slack
Where can I find the up to date information on interrupt connections in Caravel to the VexRisc CPU? ...
# caravel
k
Where can I find the up to date information on interrupt connections in Caravel to the VexRisc CPU? This page still contains instructions for the Pico CPU.
Found some documentation here. Is there a more human readable version somewhere with some high level context?
m
not eyt
I tried to put together this: https://docs.google.com/document/d/19At2TtVZSNaKqbcPY6uSJcvKjPAxnRGONdAwTsjWI9A/edit#heading=h.iwo6vjkxhgh8 to explain the difference between the pico core and the new one
@User check the link again, I pasted the wrong one
k
@User check the link again, I pasted the wrong one
Thanks! I have gone through that document already. My main question is (without understanding RISCV interrupt architecture), how do I enable the user interrupts on the CPU? There appears to be a register you have to write to enable. Perhaps a simple example would have been nice. I'll try to dig in further myself otherwise.
m
ah good question
yes, best place for that I would think would be the tests
I'm also interested in getting the docs improved so if you come up with an example please let me know
k
Sure! For mpw-6 or later, it would be good to add a user project interrupt pin test. Maybe connect the counter output to the user interrupts? For overflow/underflow conditions and a C test to show the usage of handler? This is what I'm going to do now to test our system as a start.
m
if you want to make a PR on that repo, it would be highly appreciated!
we are working on getting more coverage on the tests
k
I'll give it a go.
🤩 1
3 Views
Open in Slack
PreviousNext
Powered by

What is Linen?

Linen is a search-engine friendly community platform. We offer integrations with existing Slack/Discord communities and make those conversations Google-searchable.

Powered by