open-source-silicon.dev

IMG20220426120311.jpg

I get the following error while using the command ' make user_proj_ example' . Please tell how to rectify this.

tool unable to read your `verilog/rtl/user_proj_example.v` Check your file path

User project file is inside the /verilog/rtl . Why tool is unable to read it as it is the default location?

from which directory executing `make user_proj_example`?

From caravel user project folder. I didn't cd to openlane like before the update

If you follow quickstart guide, it should work without any issue