Hi all, could there be a case where Netgen shows a device mismatch despite all the pin names and fanouts seemingly being a perfect match?

@Noah Moroze Can you post the netgen output?

Yup, here it is!

@Noah Moroze So it looks like your creating a whole new chip (not something that goes on the google/efabless/skywater shuttle). Is that correct? As @Tim Edwards mentioned, the VSUBS disconnected layout port on asic_core is probably one problem. It looks like your 2 port sram verilog is missing

clk1

and

csb1

inputs. These should probably be tied to ground if your not using the second port. The

vssd/vssio/vccd/vddio_hvc_pad

cells have unmatched ports

DRN_HCV

and

SRC_BDY_HVC

.

@Mitch Bailey thanks for taking a look!

So it looks like your creating a whole new chip (not something that goes on the google/efabless/skywater shuttle). Is that correct?

this is correct!

Is your repo open-source?

unfortunately not able to share at the moment. However, I was able to fix the problem! The issue seems to be related to the structure of the Verilog netlist. The original netlist came directly from Yosys synthesis, but if I take that Verilog file, read it in OpenROAD, and directly write it back out, the OpenROAD output passes LVS!