@User Sometime after netgen v1.5.194, I get some problems with pins matching in some designs. I have a subcell (the precharge) with no gnd connection, but magic likes to add one for some reason. It is not connected to anything in the precharge subcell. netgen 194 and prior used to match this fine:

Subcircuit pins:
Circuit 1: precharge_0                     |Circuit 2: precharge_0
-------------------------------------------|-------------------------------------------
vdd                                        |vdd
bl                                         |bl
br                                         |br
en_bar                                     |en_bar
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes precharge_0 and precharge_0 are equivalent.

However, if I updated to a newer netgen 1.5.202, I get this:

Subcircuit pins:
Circuit 1: precharge_0                     |Circuit 2: precharge_0
-------------------------------------------|-------------------------------------------
vdd                                        |vdd
bl                                         |bl
br                                         |br
en_bar                                     |en_bar
gnd                                        |(no matching pin)
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes precharge_0 and precharge_0 are equivalent.

(Note these are with the same exact spice and extracted netlists...) This extra pin seems to cause problems later:

(no matching net)                          |Net: /bank0//port_data0//precharge_array0/
                                           |  precharge_0/proxygnd = 1
                                           |
(no matching net)                          |Net: /bank0//port_data0//precharge_array0/
                                           |  precharge_0/proxygnd = 1
                                           |
(no matching net)                          |Net: /bank0//port_data0//precharge_array0/
                                           |  precharge_0/proxygnd = 1
                                           |
(no matching net)                          |Net: /bank0//port_data0//precharge_array0/
                                           |  precharge_0/proxygnd = 1

I guess there are two possible solutions: 1. How do I get magic to not extract that pin? I'm using readspice and the spice does not have the gnd, so I'm not sure where it is coming from! 2. How can I prevent the mismatch in LVS like earlier versions.

Netgen from 1.5.194 is being more rigorous about disconnected pins, specifically to avoid other issues that were arising from having multiple port names for the same net. But I'm inclined to say that netgen is correct and magic needs to be fixed; however, I'm not completely sure on that account. The issue probably comes from magic's handling of the substrate, since the substrate exists for every circuit regardless of whether that circuit declares a ground or not. But did you set something in magic to declare the substrate node to be called "gnd"? Otherwise I'm not sure where the name "gnd" comes from in the layout. It's a bit hard to figure out in magic when the substrate isn't connected to anything at all and therefore remove it from the netlist. Especially since if the netlist contains parasitics, then there are parasitics to substrate. So it has to check that nothing is connected to substrates, and parasitics are not being generated.

@Tim Edwards Yes, my substrate is gnd

I think I can solve this but I will have to make an update to magic's ext2spice routine.

Yes I set it to gnd explicitly

Can I get an example layout? I know where ext2spice adds the "gnd" node but I need to see what about the node record would indicate that it is not connected to any devices.

The top is sram.mag, but it happens in the precharge_array module

I thought about this for a while and realized that I had considered anything a "port" that makes a connection into another circuit; but at the same time, I considered all substrate connections to be valid ports because all substrate caps are referenced to, naturally, the substrate. But that means that magic ends up making substrate a port for every subcircuit even when no devices connect to it. What I did was to make an exception when extracting for LVS (that is, running "ext2spice" with infinite capacitor threshold, so there are no parasitics to substrate) so that the substrate will only become a port of a subcircuit if at least one device connects to substrate in the subcircuit or one of the subcircuit's descendents. Clearly this could be solved in netgen as well; netgen is being a bit more rigorous than it used to about pin connections, and is now running into the problem that it sees the substrate connecting a bunch of cells together. It really needs to prune back unconnected networks. But for now, it is easier to solve the problem from magic's side.

Thanks @Tim Edwards!

Thank me after you find that it actually works as advertised and doesn't break something else. . .