In school when we did VLSI we had the schematic in multiple layers and then we started making cells of all the parts in a bottom-down style approach. So every component had at least two netlists, one schematic and one layout'd.

should that switch (use schematic or extracted) be global or per-symbol? so you decide for any symbol what to use... example, you have a schematic with 'FDQX2' flip flops and you want to switch netlisting of all these flops to use the layout-extracted/backannotated netlist?

I'm thinking per symbol would probably make the most sense, and would allow you to run duplicated parallel measurements with the two configs to compare

1. in xschem a symbol may have a 'schematic=..' attribute to bind a specific schematic definition to a symbol. Default is that for xxx.sym you use xxx.sch, however using 'schematic=' you can use any alternate schematic view for a symbol. The alternate schematic view might contain no drawings but just a plain spice netlist, for example from a layout extraction tool. I have a video for this (go to minute 4') , although the schematic switch is done there for verilog simulation, concept is valid for spice as well.

Ah cool! Will check it out! Thanks!

symbol level switch is needed to compare the schematic versus layout performance isn it. Specially when working with high frequencies, it is needed to debug or check the parasitic impact.

Yes, the more close your netlist is to the actual implementation the more accurate your simulation. Usually before a chip signoff all validation (timing checks, margins, max frequency, setup/hold violations) is done on a netlist extracted from layout, containing all parasitic elements. This can be done on a digital level (using sdf delay annotations) or spice (using extracted netlists) Mixed digital/analog designs usually do both spice and digital (verilog mostly) validation.