<@U01F36ZPD3Q> an early experimental fix for ngspice reduced memory usage from 2.2GB down to 280MB s...
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Stefan Schippers
12/10/2020, 4:01 PM@User an early experimental fix for ngspice reduced memory usage from 2.2GB down to 280MB see the thread
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Tim Edwards
12/12/2020, 10:38 PMThank you very much for engaging with Holger Vogt. This is a fantastic improvement!
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Stefan Schippers
12/13/2020, 9:25 PMmemory footprint is still a lot, but gettin better 🙂 I don't know if something can be done on the pdk side too...
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Tim Edwards
12/13/2020, 10:15 PM@Stefan Schippers: I considered writing a script that would parse a netlist and generate just the include files needed. I have something like that for the tests that run when the sky130_fd_pr library is generated, but it would need to be a bit different. The standard "sky130.lib.spice" file just loads pretty much everything. I don't know if the last update to ngspice cured the problem of loading even the models that were not called for in the argument to the .lib statement.
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Stefan Schippers
12/13/2020, 10:16 PM@Tim Edwards, will do some tests.
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Tim Edwards
12/13/2020, 10:18 PMThe previous test I did was to include "sky130.lib.spice", and then run again with a file that contained only one set of corners. The one with only the one set of corners started up much, much faster in spite of the fact that I would have expected the two cases to be identical.
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Stefan Schippers
12/13/2020, 10:55 PM@Tim Edwards this is exactly the test i did. First one uses a '.LIB ..../sky130.lib.spice tt, second one just the includes specified in the .LIB for the tt corner. The 2 cases should run in almost identical time, however:
1st case ran simulation in 91 sec and took 300MB or resident RAM during run
2nd case completed in 39 sec and took 118MB.
Doing a 'listing expand>filename' in the 2 cases generated an identical file with 1 model associated to 1 transistor (using the low memory branch prepared by Holger), so i guess lot of time is just spent parsing unneeded models, still dont know what the additional ~180MB are used for as the listing is identical in the 2 cases.
Stefan Schippers
12/13/2020, 11:31 PM@Tim Edwards i have a 8K rom macrocell simulation, this netlist contains 14.2K mos transistors ( 5800 in circuitry, rest of transistors are nmos in the (reduced) test ROM array). this simulation requires 56MB of memory. This is far better than anything i have seen on HSPICE. this sim uses however BSIM3.v3 (level=49) models without model parameters depending on other parameters depending on other parameters... , so these can be reduced. I think this makes the huge difference, the expanded listing shows 1 model line for the NMOS and 1 model line for the PMOS for the whole netlist. (the design uses only 2 transistor types). Sky130 pdk requires (during hierarchy flattening) a different model instance per transistor, as it has ''parametric'' model parameters (one single model instance can not serve all transistors of that type).
EDIT: may be in sky130 pdk we have 1 model per transistor because transistors are wrapped into subcircuits, or because model parameters are derived from subcircuit instance parameters or both.. I don't know, by now...
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